STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 99

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

6.4.4.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in
6-29. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
The
implementation. The exact timing constraints are
Note: The value of 22 Ohms corresponds to tracks with Z
Figure 6-30
HCLK
PCICLKO
PCICLKI
PCICLKx
describes a typical clock delay
PCICLKO
PCICLKI
Figure 6-29. Typical PCI clock routing
Figure 6-30. Clocks relationships
Issue 1.0 - July 24, 2002
Figure
0
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum
clock skew between all devices is 2ns according
to PCI specifications.
listed in the PCI section of the Electrical
Specifications Chapter.
= 70 Ohms.
PCICLKA
PCICLKB
PCICLKC
DESIGN GUIDELINES
Device A
Device B
Device C
99/111