STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 50

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure
characteristics of the SDRAM interface. The
Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
The PC100 memory is recommended to reach
90MHz operation.
50/111
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK not activated
Toutput
Tsetup
Tdelay
Tcycle
MCLKx
MCLKI
STPC.output
STPC.input
Name
Thigh
Thold
Tlow
4-5,
Table
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to RAS# Valid
MCLKI to CAS# Valid
MCLKI to CS# Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MCLKI to MA[ ] Outputs Valid
MCLKI to MWE# Valid
MD[63:0] setup to MCKLI
MD[63:0] hold from MCKLI
4-10,
T
Table 4-11
hold
T
delay
Figure 4-5. SDRAM Timing Diagram
lists the AC
T
Issue 1.0 - July 24, 2002
output (max)
T
high
MCLKx clocks are the input clock of the SDRAM
devices.
T
cycle
T
setup
T
T
output (min)
low
-0.36
1.35
1.35
Min
1.6
1.6
1.6
1.6
1.6
7.5
10
4
4
Typ
2.1
Max
5.2
5.2
5.2
5.2
5.2
5.2
5.2
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns