STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 35

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

3.1. STRAP OPTION REGISTER DESCRIPTION
3.1.1. STRAP REGISTER 0
This register is read only.
Bit Number Sampled
STRAP0
MD[7]
7
Bits 7-6
Bits 5-4
Bits 1-0
Bit 3
Bit 2
MD[6]
6
This register defaults to the values sampled on the MD pins after reset
MD[4], MD[17]
Mnemonic
MD[7:6]
MD[9:8]
MD[5]
Rsv
MD[9]
5
Access = 0022h/0023h
Description
PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK
PLL programming according to the PCICLK frequency.
MD7 MD6
Mode selection:
MD9 MD8
Reserved
Host Memory synchronization. This bit reflects the value sampled on
[MD5] and controls the MCLK/HCLK synchronization.
PCICLK division: These bits reflect the values sampled on [MD4] and
MD[17] to select the PCICLK frequency.
MD4 MD17
Issue 1.0
0
0
1
0
0
1
1
0: MCLK and HCLK not synchronized
1: MCLK and HCLK synchronized.
0
1
1
MD[8]
4
0
1
X
0 ISA mode: ISA enabled, PCMCIA & Local Bus disabled
1 PCMCIA mode: PCMCIA enabled, ISA & Local Bus disabled
0 Local Bus mode: Local Bus enabled, ISA & PCMCIA disabled
1 Reserved
X
0
1
- July 24, 2002
PCICLK frequency between 16 & 32 MHz
PCICLK frequency between 32 & 64 MHz
PCI Clock output = HCLK / 3
PCI Clock output = HCLK / 2
Reserved
PCI Clock output = HCLK / 4
RSV
3
MD[5]
2
MD[4]
1
STRAP OPTION
Regoffset =04Ah
MD[17]
0
35/111