STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 5

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

1. GENERAL DESCRIPTION
At the heart of the STPC Atlas is an advanced
processor block that includes a powerful x86
processor core along with a 64-bit SDRAM
controller, advanced 64-bit accelerated graphics
and video controller, a high speed PCI bus
controller and industry standard PC chip set
functions (Interrupt controller, DMA Controller,
Interval timer and ISA bus).
The STPC Atlas has in addition, a TFT output, a
Video Input, an EIDE controller, a Local Bus
interface, PCMCIA and super I/O features
including USB host hub.
1.1. ARCHITECTURE
The STPC Atlas makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main
memory and graphics frame-buffer. This means a
reduction in total system memory for system
performances that are equal to that of a
comparable frame buffer and system memory
based system, and generally much better, due to
the
attaching the graphics engine directly to the 64-bit
processor host interface running at the speed of
the processor bus rather than the traditional PCI
bus.
The 64-bit wide memory array provides the
system with an 800MB/s peak bandwidth. This
allows for higher resolution screens and greater
color depth. The processor bus runs at 133 MHz,
further increasing “standard” bandwidth by at least
a factor of two.
The ‘standard’ PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor
functions such as communication ports are
accessed by the STPC Atlas via an internal ISA
bus.
The PCI bus is the main data communication link
to the STPC Atlas chip. The STPC Atlas translates
appropriate host bus I/O and Memory cycles onto
the PCI bus. It also supports the generation of
Configuration cycles on the PCI bus. The STPC
Atlas, as a PCI bus agent (host bridge class), is
compatible with PCI specification 2.1. The chip-
set also implements the PCI mandatory header
registers in Type 0 PCI configuration space for
easy porting of PCI aware system BIOS. The
device contains a PCI arbitration function for three
external PCI devices.
Figure 1-1
higher
describes this architecture.
core;
memory
additional
bandwidth
low
allowed
bandwidth
Issue 1.0 - July 24, 2002
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1.2. GRAPHICS FEATURES
Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or off-
screen frame buffer areas of SDRAM memory.
The frame buffer can occupy a space up to 4
Mbytes anywhere in the physical main memory.
The maximum graphics resolution supported is
1280 x 1024 in 16 Million colours at 75 Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
To generate the TFT output, the STPC Atlas
extracts the digital video stream before the
RAMDAC and reformats it to the TFT format. The
height
programmable.
1.3. INTERFACES
An industry standard EIDE (ATA 2) controller is
built in to the STPC Atlas and connected internally
via the PCI bus.
The STPC Atlas integrates two USB ports.
Universal Serial Bus (USB) is a general purpose
communications
peripherals to a PC. The USB Open Host
Controller Interface (Open HCI) Specification,
revision 1.1, supports speeds of up to 12 MB/s.
USB is royalty free and is likely to replace low-
speed legacy serial, parallel, keyboard, mouse
and floppy drive interfaces. USB Revision 1.1 is
fully supported under Microsoft Windows 98 and
Windows 2000.
The STPC Atlas PCMCIA controller has been
specifically designed to provide the interface with
PCMCIA cards which contain additional memory
or I/O
The power management control facilities include
socket power control, insertion/removal capability,
power saving with Windows inactivity, NCS
controlled Chip Power Down, together with further
controls for 3.3V suspend with Modem Ring
Resume Detection.
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GENERAL DESCRIPTION
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