MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 15

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

D52
HCS1
D53
HRW
HRD/HRD
D54
HDS/HDS
HWR/HWR
D55
HREQ/HREQ
HTRQ/HTRQ
Signal
Table 1-4.
Input/Output
Input
Input/Output
Input
Input
Input/Output
Input
Input
Input/Output
Output
Output
Data Flow
System Bus, HDI16, and Interrupt Signals (Continued)
Data Bus Bit 52
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Chip Select
When the HDI16 interface is enabled, this is one of the two chip-select pins. The
HDI16 chip select is a logical OR of HCS1 and HCS2.
Data Bus Bit 53
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Read Write Select
When the HDI16 interface is enabled in Single Strobe mode, this is the read/write
input (HRW).
Host Read Strobe
When the HDI16 is programmed to interface with a double data strobe host bus,
this pin is the read data strobe Schmitt trigger input (HRD/HRD). The polarity of the
data strobe is programmable.
Data Bus Bit 54
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Data Strobe
When the HDI16 is programmed to interface with a single data strobe host bus, this
pin is the data strobe Schmitt trigger input (HDS/HDS). The polarity of the data
strobe is programmable.
Host Write Data Strobe
When the HDI16 is programmed to interface with a double data strobe host bus,
this pin is the write data strobe Schmitt trigger input (HWR/HWR). The polarity of
the data strobe is programmable.
Data Bus Bit 55
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Request
When the HDI16 is programmed to interface with a single host request host bus,
this pin is the host request output (HREQ/HREQ). The polarity of the host request
is programmable. The host request may be programmed as a driven or open-drain
output.
Transmit Host Request
When the HDI16 is programmed to interface with a double host request host bus,
this pin is the transmit host request output (HTRQ/HTRQ). The signal can be
programmed as driven or open drain. The polarity of the host request is
programmable.
3
3
3
3
3
3
3
System Bus, HDI16, and Interrupt Signals
Description
1-11