MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 17

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Reserved
DP0
EXT_BR2
IRQ1
DP1
EXT_BG2
IRQ2
DP2
EXT_DBG2
IRQ3
DP3
EXT_BR3
Signal
Table 1-4.
Input
Input/Output
Input
Input
Input/Output
Output
Input
Input/Output
Output
Input
Input/Output
Input
Data Flow
System Bus, HDI16, and Interrupt Signals (Continued)
The primary configuration is reserved.
Data Parity 0
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity zero pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 0 and D[0–7].
External Bus Request 2
An external master asserts this pin to request bus ownership from the internal
arbiter.
Interrupt Request 1
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 1
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity one pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 1 and D[8–15].
External Bus Grant 2
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
Interrupt Request 2
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 2
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity two pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 2 and D[16–23].
External Data Bus Grant 2
The MSC8101 asserts this pin to grant data bus ownership to an external bus
master.
Interrupt Request 3
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 3
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity three pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 3 and D[24–31].
External Bus Request 3
An external master asserts this pin to request bus ownership from the internal
arbiter.
1
1
1
1
1
1
1
1,2
1,2
1,2
System Bus, HDI16, and Interrupt Signals
1,2
Description
1-13