MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 62

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

AC Timings
2-12
Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to
sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800
reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all
the clocks to the MSC8103 are enabled. If the DLLDIS bit in the reset configuration word is reset, the
DLL starts the locking process after the SPLL is locked. During PLL and DLL locking,
SRESET
SRESET
DLL is bypassed and there is no locking process, thus saving the DLL locking time. Figure 2-4 shows
the power-on reset flow.
Output (I/O)
Output (I/O)
PORESET
PORESET
HRESET
SRESET
Internal
Input
are asserted.
is released three bus clocks later. If the DLLDIS bit in the reset configuration word is set, the
asserted for
CLKIN.
min 16
1
HRESET
Figure 2-4. Hardware Reset Configuration Timing
In reset configuration mode:
reset configuration sequence
occurs in this period.
RSTCONF is sampled for
master/slave determination
remains asserted for another 512 BUS clocks and is then released. The
2
PLL locked
800 SPLLMFCLKs. DLL
locks 3073 bus clocks after
PLL is locked.
When DLL is disabled, reset
period is shortened by 3073
bus clocks.
PLL locks after
MODCK[1–3] are sampled.
MODCK_H bits are ready
for PLL.
3
DLL locked
4
HRESET/SRESET are
extended for 512/515 bus
clocks, respectively, from PLL
and DLL Lock time.
MODCK[1–3]
6
5
HRESET
, which are
and