MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 5

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MSC8103M1100

Manufacturer Part Number
MSC8103M1100
Description
Network Processor, Networking Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet

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Chapter 1
Signal/
Connection
Descriptions
1.1 Signal Groupings
The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1,
and Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each group,
and references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1
shows MSC8101 external signals organized by function. Figure 1-2 indicates how the parallel
input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the
MSC8103 Communications Processor Module (CPM) is a subset of the parallel I/O signals supported by
the MPC8260 device, port pins are not numbered sequentially.
Power (V
Clock
Reset, Configuration, and EOnCE
Memory Controller
Communications Processor Module (CPM)
Input/Output Parallel Ports
JTAG Test Access Port
Reserved (denotes connections that are always reserved)
System Bus, HDI16, and Interrupts
CC
, V
DD
, and GND)
Functional Group
Table 1-1.
MSC8103
Functional Signal Groupings
Port A
Port B
Port C
Port D
Connections
Number of
Signal
133
80
11
27
26
14
18
6
8
5
5
Detailed Description
Table 1-2 on page 1-16
Table 1-3 on page 1-19
Table 1-4 on page 1-26
Table 1-5 on page 1-31
Table 1-6 on page 1-41
Table 1-7 on page 1-44
Table 1-8 on page 1-45
Table 1-1 on page 1-4
Table 1-2 on page 1-5
Table 1-3 on page 1-6
Table 1-4 on page 1-8
1-1

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