MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 61

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.7.2.3 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after
PORESET
signals described in Table 2-12 one the rising edge of
If HPE is sampled high, the host port is enabled. In this mode the
device extends the internal
host must write four 8-bit half-words to the Host Reset Configuration Register address to program the
reset configuration word, which is 32 bits wide. For more information, see the MSC8103 Reference
Manual. The reset configuration word is programmed before the internal PLL and DLL in the MSC8103
are locked. The host must program it after the rising edge of the
must have its own clock that does not depend on the MSC8103 clock. After the PLL and DLL are locked,
HRESET
bus clocks later (see Figure 2-3).
2.7.2.4 Hardware Reset Configuration
Hardware reset configuration is enabled if HPE is sampled low at the rising edge of
driven on
configuration. If
configuration slave. If
as a configuration master. Section 2.7.2.4, Hardware Reset Configuration, explains the configuration
sequence and the terms “configuration master” and “configuration slave.”
Directly after the deassertion of
master or configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts
HRESET
takes 1024
mode.
Output (I/O)
Output (I/O)
PORESET
PORESET
HRESET
SRESET
Internal
remains asserted for another 512 bus clocks and is then released. The
and
Input
RSTCONF
is deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the
CLOCKIN
SRESET
asserted for
RSTCONF
CLKIN.
min 16
1
while
cycles, after which
RSTCONF
throughout the power-on reset process, including configuration. Configuration
PORESET
Any time
Figure 2-3. Host Reset Configuration Timing
PORESET
is deasserted (driven high) while
RSTCONF, HPE
HRM, BTM
pins are sampled
PORESET
Reset Configuration
is asserted (driven low) while
Host programs
2
until the host programs the reset configuration word register. The
Word
changes from assertion to deassertion determines the MSC8103
MODCK[1–3]
and choice of the reset operation mode as configuration
PLL locked
PLL locks after
800 SPLLMFCLKs and
DLL locks 3073 BUS clocks
after PLL is locked.
When DLL is disabled,
reset period is shortened by
DLL lock time.
MODCK[1–3] pins
are sampled.
MODCK_H bits
PORESET
are ready for PLL.
are sampled to determine the MSC8103 working
3
PORESET
PORESET
PORESET
DLL locked
when the signal is deasserted.
RSTCONF
4
changes, the MSC8103 acts as a
input. In this mode, the host
changes, the MSC8103 acts
pin must be pulled up. The
HRESET/SRESET are
extended for 512/515 BUS
clocks, respectively, from PLL
and DLL lock
SRESET
PORESET
5
6
is released three
. The value
2-11