MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 47

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PD18
PD17
PD16
I/O
FCC1: RXADDR4
UTOPIA master
FCC1: RXADDR4
UTOPIA slave
FCC1: RXCLAV3
UTOPIA multi-PHY master,
direct polling
SPI: SPICLK
BRG2O
FCC1: RXPRTY
UTOPIA
SPI: SPIMOSI
FCC1: TXPRTY
UTOPIA
SPI: SPIMISO
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-6. Port D Signals (Continued)
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input
Input
Input
Communications Processor Module (CPM) Ports
FCC1: UTOPIA Master Receive Address Bit 4
In the ATM UTOPIA master interface supported by FCC1
using multiplexed polling, this is receive address bit 4.
FCC1: UTOPIA Slave Receive Address Bit 4
In the ATM UTOPIA slave interface supported by FCC1,
this is the receive address bit 4.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available
3 Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, RXCLAV3 is asserted by an external
PHY when one complete ATM cell is available for transfer.
SPI: Clock
The SPI interface comprises four signals: master out slave
in (SPIMOSI), master in slave out (SPIMISO), clock
(SPICLK) and select (SPISEL). The SPI can be configured
as a slave or master in single- or multiple-master
environments. SPICLK is a gated clock, active only during
data transfers. Four combinations of SPICLK phase and
polarity can be configured. When the SPI is a master,
SPICLK is the clock output signal that shifts received data in
from SPIMISO and transmitted data out to SPIMOSI.
Baud Rate Generator 2 Output
The CPM supports up to 8 BRGs. The BRGs can be used
internally to the MSC8103 and/or provide an output to one
of the 8 BRG pins.
FCC1: UTOPIA Receive Parity
In the ATM UTOPIA interface supported by FCC1, this is
the odd parity bit for RXD[0–7].
SPI: Master Output Slave Input
The SPI interface comprises our signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK)
and select (SPISEL). The SPI can be configured as a slave
or master in single- or multiple-master environments. When
the SPI is a slave, SPICLK is the clock input that shifts
received data in from SPIMOSI and transmitted data out
through SPIMISO.
FCC1: UTOPIA Transmit Parity
In the ATM UTOPIA interface supported by FCC1, this is
the odd parity bit for TXD[0–7].
SPI: Master Input Slave Output
The SPI interface comprises four signals: master out slave
in (SPIMOSI), master in slave out (SPIMISO), clock
(SPICLK), and select (SPISEL). The SPI can be configured
as a slave or master in single- or multiple-master
environments. When the SPI is a slave, SPICLK is the clock
input that shifts received data in from SPIMOSI and
transmitted data out through SPIMISO.
Description
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