MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 20

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Memory Controller Signals
1.6 Memory Controller Signals
1-16
Refer to the Memory Controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for
detailed information about configuring these signals.
CS[0–7]
BCTL1
BADDR[27–28]
ALE
BCTL0
PWE[0–7]
PSDDQM[0–7]
PBS[0–7]
PSDA10
PGPL0
PSDWE
PGPL1
Signal
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Data
Flow
Table 1-2. Memory Controller Signals
Chip Select
Enable specific memory devices or peripherals connected to MSC8101 buses.
Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of
this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit
(SIU) chapter in the MS8103 Technical Reference manual for details.
Burst Address 27–28
Two of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8101 memory controller.
Address Latch Enable
Controls the external address latch used in external master bus configuration.
Buffer Control 0
Controls buffers on the data bus. The exact function of this pin is defined by the
value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the
MS8103 Technical Reference manual for details.
Bus Write Enable
Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins
select byte lanes for write operations.
Bus SDRAM DQM
Outputs of the SDRAM control machine. These pins select specific byte lanes of
SDRAM devices.
Bus UPM Byte Select
Outputs of the User-Programmable Machine (UPM) in the memory controller.
These pins select specific byte lanes during memory operations. The timing of
these pins is programmed in the UPM. The actual driven value depends on the
address and size of the transaction and the port size of the accessed device.
Bus SDRAM A10
Output from the bus SDRAM controller. This pin is part of the address when a row
address is driven. It is part of the command when a column address is driven.
Bus UPM General-Purpose Line 0
One of six general-purpose output lines of the UPM. The values and timing of this
pin are programmed in the UPM.
Bus SDRAM Write Enable
Output from the bus SDRAM controller. This pin should connect to the SDRAM WE
input signal.
Bus UPM General-Purpose Line 1
One of six general-purpose output lines from the UPM. The values and timing of
this pin are programmed in the UPM.
Description