MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 25

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PA25
PA24
PA23
PA22
PA21
I/O
FCC1: TXD0
UTOPIA
SDMA: MSNUM0
FCC1: TXD1
UTOPIA
SDMA: MSNUM1
FCC1: TXD2
UTOPIA
FCC1: TXD3
UTOPIA
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
Peripheral Controller:
Name
Dedicated Signal
Protocol
Table 1-3. Port A Signals (Continued)
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
Output
Communications Processor Module (CPM) Ports
FCC1: UTOPIA Transmit Data Bit 0
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 outputs ATM cell octets (UTOPIA interface data)
on TXD[0–7]. TXD7 is the most significant bit. TXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes.
Module Serial Number Bit 0
MSNUM[0–4] of is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates
which section, transmit (0) or receive (1), is active during
the transfer.
FCC1: UTOPIA Transmit Data Bit 1
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 outputs ATM cell octets (UTOPIA interface data)
on TXD[0–7]. TXD7 is the most significant bit. TXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes.
Module Serial Number Bit 1
MSNUM[0–4] of is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates
which section, transmit (0) or receive (1), is active during
the transfer.
FCC1: UTOPIA Transmit Data Bit 2
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: UTOPIA Transmit Data Bit 3
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: UTOPIA Transmit Data Bit 4
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1.
TXD3 is the most significant bit. TXD0 is the least significant
bit.
Description
1-21