MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 55

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.6.2 Clocks Programming Model
This section describes the clock registers in detail. The registers discussed are as follows:
• System Clock Control Register (SCCR)
• System Clock Mode Register (SCMR)
2.6.2.1 System Clock Control Register
RESET
RESET
The SCCR is memory-mapped into the SIU register map of the MSC8103.
TYPE
TYPE
CLKODIS
Bit
Bit
Bit No.
DFBRG
Name
28–29
30–31
0–26
27
—
—
16
0
PORESET
17
1
01
—
—
0
Figure 2-1. System Clock Control Register (SCCR)—0x10C80
Defaults
18
2
Unaffected CLKOUT Disable
Unaffected Division Factor for the BRG Clock
19
3
Reset
Hard
—
—
20
4
Table 2-7. SCCR Bit Descriptions
Reserved
Reserved. Write to 0 fro future compatibility.
Disables the CLKOUT signal. The value of
CLKOUT when disabled is indeterminate
(can be 1 or 0).
Reserved. Write to 0 fro future compatibility.
Defines the BRGCLK frequency. Changing
this value does not result in a loss of lock
condition.
21
—
—
5
22
6
23
Description
7
Reserved
—
—
24
8
25
9
10
26
CLKODIS
R/W
11
27
0
0
1
00
01
10
11
CLKOUT enabled (default)
CLKOUT disabled
Divide by 4
Divide by 16 (default value)
Divide by 64
Divide by 256
Clock Configuration
12
28
Reserved
—
—
Settings
13
29
14
30
0
DFBRG
R/W
15
31
1
2-5