MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 27

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
3) If an underflow condition occurs, then the device
4) A collision on the D-channel will cause a TE
5) Once the closing flag of the last packet in the Tx
On the receiving side, packets should be processed
in the following way:
1) An interrupt is issued through the RxFF bit in the
2) If an interrupt indicating an overflow condition is
3) The detection of a closing flag causes an
4) Receiving a frame abort sets the EOPD and FA
9.5 Hints on Passive Bus Configuration
In a passive bus configuration, there are certain
procedures that all TEs on the line should follow to
avoid contention and to provide fair access among
all. Some of these procedures are listed as follows:
should be written to the Tx FIFO within 2 ms to
avoid an underflow condition. Additional 15
bytes can be added to the Tx FIFO.
will abort the last packet automatically and an
interrupt will be issued through the TxFun bit in
the HDLC Interrupt Status Register. The packet
should be retransmitted again.
SNIC to generate an interrupt through the Dcoll
bit and to ignore the remaining bytes of the
packet. The user should then retransmit the
packet.
FIFO is transmitted, the SNIC issues an interrupt
through the TEOP bit. The user may then repeat
the procedure starting from step 1 if more
packets are to be transmitted.
HDLC Interrupt Status Register whenever 15
bytes have accumulated in the Rx FIFO. This is
a warning indicating that the Rx FIFO should be
read within 2.5 ms before it overflows.
detected (RxFov bit is set to 1), then the last
packet that was not closed with a flag before the
overflow occurred should be ignored.
interrupt through the EOPD bit of the HDLC
Interrupt Status Register. The remaining bytes of
the corresponding packet in the Rx FIFO should
be read while monitoring the status of each byte
by checking the two RxByte Status bits in the
HDLC Status Register. These two bits indicate
which byte is the last of the packet and whether
the Frame Check Sequence (FCS) of this packet
is good or bad.
bits to 1 thus causing an interrupt. The SNIC will
assign a bad FCS word to the aborted packet
allowing the processing of this interrupt in the
same manner as in step 3 above.
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10.0 CONCLUSION
As seen throughout this application note, the SNIC is
a fully featured Subscriber Network Interface Circuit
for the ISDN S/T interface. The objective of this note
was to define some of the basic rate interface
requirements as outlined in the CCITT I.430 and
ANSI T1.605, and reveal how these functions were
implemented on the SNIC.
The system interfaces to the SNIC were discussed to
identify access procedures to the various internal
registers using the ST-BUS and the microport. In
addition, the internal timing used to transfer data
within the silicon was discussed in order to calculate
the throughput delay of the system to line, and line to
system.
determine the total delay introduced by the SNIC.
Finally, further explanation was given on the HDLC
formatter. Packet structure and Tx and Rx FIFO were
discussed to identify chip response during fault
conditions.
When a TE has no layer 2 frames to transmit, it
A TE should send binary ONEs in any B-channel
When multiframing is declared, a TE which is not
For a point-to-multipoint wiring configuration, the
shall send binary ONEs on the D-channel. In
other words, the interframe time fill on the D-
channel in the TE-to-NT direction should be all
binary ONEs. This can be done by setting the
IFTF bit of HDLC Control Register 1 to logic 0. In
this manner, other TEs will have an opportunity
to access the D-channel using the priority
mechanism circuitry.
which is not assigned to it. The user can put
channels B1 or B2 in an all ONEs idle code by
disabling the corresponding port of DSTi stream
through the ST-BUS Control Register.
using the Q-bits should set them to binary ONE.
Since the binary value of every Q-bit is
determined by that of the TxMCH bit of the TE
Mode C-channel Control Register, a TE which is
not using the Q-bits should set the TxMCH bit to
1 while multiframing is active. A TE that does not
follow this procedure will cause contention on
the Q-channel with other TEs.
user must maintain the wiring polarity integrity of
the interchange circuit in the direction of TE-to-
NT among all TEs. If this is not done, then
collision will occur in bits common to all TEs
such as the framing bit F.
This
allows
the
system
MSAN-141
designer
A-227
to