MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 3

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
1.0 MT8930B/31B S/T-Interface
The MT8930B/31B Subscriber Network Interface
Circuit (SNIC) is a multifunction transceiver providing
a complete interface to the S/T Reference Point as
specified in CCITT Recommendation I.430 and ANSI
T1.605.
point-to- multipoint voice/data transmission, the
SNIC may be used at either end of the digital
subscriber loop. A programmable digital interface
allows the MT8930B/31B to be configured as a
Network
Equipment (TE) device.
The physical medium for the S-interface is a
balanced line for each direction of transmission
capable of supporting 192 kbit/s which will now be
referred to as the S-Bus. This transmission facility is
time division multiplexed in order to carry 2 x 64
kbit/s B-channels and 1 x 16 kbit/s D-channel.
Transmission capability for both B and D channels,
as well as related timing and synchronization
functions, are provided on chip. The signalling
capability and procedures necessary to enable
customer terminals (TEs) to be activated and
deactivated
functionality. The SNIC handles D-channel resource
allocation and prioritization for access contention
resolution and signalling requirements in passive bus
line configurations. Control and status information
allows implementation of maintenance functions and
monitoring of the device and the subscriber loop.
An HDLC transceiver is included on the SNIC for link
access
Depacketized data is passed to and from the
transceiver via the microprocessor port. Two 19 byte
deep FIFOs, one for transmit and one for receive, are
provided to buffer the data. The HDLC block can be
set up to transmit or receive to/from either the
S-interface port or the ST-BUS port. Further, the
transmit destination and receive source can be
independently selected, e.g., transmit to S-interface
while receiving from ST-BUS. The transmit and
receive paths can be separately enabled or disabled.
Both one and two byte address recognition is
supported by the SNIC. A transparent mode allows
data to be passed directly to the D-channel without
being packetized.
The MT8930B provides a controllerless mode which
eliminates the need for a microprocessor. The TE
mode in the MT8930B is selected by tying pin 8 to
ground, or to a 4.096 MHz clock. On the other hand,
the MT8931B doesn’t offer a controllerless mode, but
its TE mode is selected by either tying pin 8 to a
Transceiver
protocol
Implementing
Termination
form
handling
part
(NT)
both
of
via
the
or
point-to-point
as
the
MT8930B/31B’s
a
D-channel.
Terminal
and
4.096 MHz clock or to a crystal connected between
pin 8 and pin 7.
The MT8930B is recommended as a replacement for
the MT8930 in existing systems, or for new
proprietary applications where CCITT and ANSI
standards don’t have to be fully met. In such cases,
customers may operate the MT8930B in TE mode
without the use of an external clock, therefore,
saving the added cost of an external oscillator.
The MT8931B, on the other hand, is recommended
for new designs requiring full compatibility with
CCITT and ANSI standards. The MT8931B will
operate in TE mode with just a crystal, as compared
to an oscillator for the MT8930B.
2.0 Access Considerations at the S-
2.1
The line code used on the S-interface is a pseudo
ternary code with 100% pulse width as shown in
Figure 2 below. Binary zeros are represented as
marks on the line and successive marks will
alternate in polarity. A mark which does not adhere
to the alternating polarity is known as a bipolar
violation.
2.2
A valid S-Bus frame consists of 48 bits transmitted at
the nominal bit rate of 192 kbit/s. This gives a 4 kHz
S-Bus frame of which each B- or D-channel will
consume two valid timeslots. The frame is struc-
tured using various bits which are used as follows:
F-bit: The F-bit is used to delimit the S-Bus frame
Fa-bit: The Fa-bit is the auxiliary framing bit. It is
BINARY
VALUE
LINE
SIGNAL
Figure 2 - Alternate Zero Code Inversion Line
Interface
Line Code
Frame Structure
boundary. The F-bit is positioned at the
beginning of the frame and it can be iden-
tified very quickly because it will always be a
mark which will violate the alternate line code
sequence. (i.e., F-bit is a violation).
used to secure the frame position in the
presence of an idle B- and D-channel
following the F-bit. The Fa and N bits can
0
1
0
0
0
1
MSAN-141
0
Violation
0
1
1
A-203