MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 23

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
Fig. 27 - Single-Packet Transmission Algorithm
N
Transmitter
Enable
Transmitter
Transmitter
Tx FIFO
Enabled
Enable
Full
?
?
Y
N
Y
N
N
N
Write to Tx FIFO
Transmitter
Transmitter
Tag EOP
Transmit
Enabled
Interrupt
Packet?
Disable
a new
Abort
Byte?
EOP
Set?
Stop
Start
Last
?
?
Y
N
Y
Y
N
Y
Tag FA
Structuring the received packet into a valid message
is performed using the relevant status bits from the
HDLC status register. All the bytes written to the
receive FIFO are flagged with two status bits. The
status bits are found in the HDLC status register and
indicate whether the byte to be read from the FIFO is
the first byte of the packet, the middle of the packet,
the last byte of the packet with good FCS, or the last
byte of the packet with bad FCS or an abort
sequence. This status indication is valid for the byte
which is to be read from the Receive FIFO. A simple
algorithm for receiving a packet is provided in Figure
28.
8.2
As stated above, the SNIC has two 19 byte deep
FIFOs for the reception and transmission of data
over the D-channel. Associated with the FIFOs is an
HDLC Status Register which carries the Rx and Tx
FIFO status as revealed in Tables 8 and 9.
Critical status information, such as the RxFIFO
overflow, RxFIFO full, TxFIFO full and TxFIFO
underrun have related interrupt signals to avoid
having to continuously poll the status register. These
interrupt signals must be unmasked through the
HDLC Interrupt Mask Register before they become
active.
If the received FIFO overflows, any attempt to load
more information to the full FIFO will be ignored until
the RxFIFO is read. An RxFIFO overflow will
introduce a corruption in the sequential flow in the
packet which will result in a bad FCS. However, any
attempt to write to a full TxFIFO will not overwrite the
last byte in the FIFO and cause the byte to be lost.
Conversely, if the transmit FIFO underruns, the
HDLC transmitter will begin sending an abort
sequence (01111111) followed by the selected
interframe time fill.
B5
B3
0
0
1
1
0
0
1
1
FIFOs
B4
B2
0
1
0
1
0
1
0
1
RxFIFO Empty
RxFIFO Overflow
TxFIFO Full
TxFIFO Empty
14 Bytes
15 Bytes
5 Bytes
4 Bytes
Table 8. RxFIFO Status
Table 9. TxFIFO Status
RxFIFO Status
TxFIFO Status
MSAN-141
A-223