MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 16

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

MSAN-141
Since the same physical register is used to receive
data from the ST-BUS and transmit this information
to the S-Bus, the register can not be accessed while
the information of the register is being shifted in or
out of the line or system ports. Therefore, the New
Data Available
MT8930B/31B
to
output on the IRQ, NDA pin only if this feature
is enabled through B2 of the master control register
(B2=1). In certain applications, the timing constraint
placed on the microprocessor access to the various
registers may leave insufficient time to access all
relevant registers. In this situation, specific registers
can be accessed outside the NDA window. The
timing for these registers is provided in Figure 14.
4.1.2.2
The asynchronous registers, on the other hand, are
those registers which may be accessed at any time.
These registers are mainly used to establish the
mode of the microport or to manipulate the HDLC
formatter.
4.1.3
When using the B-channels for PCM voice, the first
bit to be transmitted on the S-Bus should be the sign
bit.
standards which transmit PCM voice as most
significant bit first. However, if the B-channels are to
carry data, the bit ordering must be reversed to
Note: Type A: includes writing to DSTo, D, C, B1, and B2; and reading from the S-Bus RxD, B1, and B2.
A-216
1
2
3
F0b
DSTi/o
NDA
all synchronous registers.
This
Type B: includes writing to the S-Bus Tx B1 channel.
Type C: includes writing to the S-Bus Tx B2, and D; and reading from DSTi D, C, B1, and B2.
Synchronous Access Type A
Synchronous Access Type B
Synchronous Access Type C
Bit Orders
Asynchronous Access
complies
Characteristics
(NDA) signal is generated from the
which
with
will
the
guarantee
The NDA signal is
existing
Figure 14 - Synchronous Access Timing
telecom
Sym
t
t
t
access
SAA
SAB
SAC
Min
t
SAA
t
comply with the existing datacom standards (i.e.,
least significant bit first).
These contradicting standards place a restriction on
all information input and output through the serial
and parallel ports. Information transferred through
the serial ports, will maintain the integrity of the bit
order. Data sent to either serial port from the parallel
port, will transmit the least significant bit first.
Therefore,
microprocessor port must be reordered to have the
sign bit as the least significant bit.
The D-channel received on DSTi must be ordered
with the least significant bit first as shown in Figure
13. This also applies to the D-channel directed to
DSTo from the microprocessor port.
The C-channel bit mapping from the parallel port to
the ST-BUS is organized such that the most
significant bit is transmitted or received first.
4.2
This option is available only in the MT8930B. It
allows the SNIC to function without the need of a
controlling processor. The C
select input to the multiplexer. When C
the micro port reverts to the 8 bit multiplexed bus
microprocessor port with all relevant timing inputs.
When C
selected and the parallel port reverts to a hardwired
control/status port.
SAB
124.75
109.3
62.5
Typ
Controllerless Mode
mode
t
SAC
a
Max
is low, the controllerless mode is
PCM
Units
s
s
s
byte
mode
Application Note
input
Test Conditions
pin is used as the
through
mode
is high,
the