MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 12

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

MSAN-141
This implies that the NT must be capable of
extracting data from different sources arriving with
variable delays. For this reason, the adaptive timing
circuit mentioned above, must be disabled so that
the receiver will not try to track the differential delays.
(The adaptive timing circuit can be disabled by
setting the Timing bit (B4) of the NT C-channel
Control Register to a binary 0). The variable delay
introduced from the various sources must not exceed
a single bit period (in the presence of jitter). This
delay, coupled with the built-in offset of two bits, sets
the maximum round trip delay at 10 to 14 sec. This
restriction sets the maximum operational distance
from the NT in the order of 100 to 200 meters
depending upon cable characteristics.
2.6.3 Extended Passive Bus
A third wiring configuration is a compromise between
the point-to-point and the short passive bus (refer to
Fig. 9). This wiring configuration, known as the
extended passive bus, is a multidrop line which can
extend up to 500 meters in length. The concept
behind the extended bus is to limit the differential
round trip delays between the TEs to 2 s. This
restricts the positioning of the TEs to a cluster or
grouping of terminals at the far end of the cable
having differential distance of 0-50 meters.
2.6.4 Star
For applications which require a multidrop bus
expanded
configuration can be implemented to increase the
line length of the extended passive bus. The core of
the star configuration (refer to Figure 10) is a cluster
of NTs all tied together via the star pin. This will allow
A-212
BIT CELLS
over
ST-BUS
F0b
C4b
an
Channel
0
Channel 31
extended
Figure 12 - Clock & Frame Alignment for ST-BUS Streams
Bit 0
Channel
1
range,
Bit 7
Channel 0
Channel
Figure 11 - ST-BUS Stream Format
Bit 7
2
Bit 6
a
125 s
Bit 5
star
• • •
Channel 0
Bit 6
Bit 6
the NT to operate any loop configuration except the
information present on the S-Bus will be reflected to
all other NTs. This implies that the information
transmitted by the TE on any branch of the STAR will
be received by all the NTs as if they were all on the
same physical S-Bus. All activation and access
contention will operate normally.
3.0 SYSTEM INTERFACE
The system interface to the MT8930B/31B is the
“Serial Telecom” Bus or better known as the ST-BUS.
The ST-BUS is a synchronous time division
multiplexed serial bussing scheme with data streams
operating at 2048 kbit/s configured as 32 X 64 kbit/s
channels (refer to Figure 11).
3.1
Synchronization of the data transfer on the ST-BUS
is provided from a frame pulse which identifies the
frame boundaries and repeats at an 8 kHz rate.
(Figure 12 shows how the frame pulse (F0b) defines
the ST-BUS frame boundaries.)
into the device on the rising edge of the 4096 kHz
clock (C4b) three quarters of the way into the bit cell,
while data is clocked out on the falling edge of the
4096 kHz clock at the start of the bit cell.
All timing signals (i.e., F0b & C4b) are bidirectional
denoted by the terminating b). The I/O configuration
of these pins is controlled by the mode of operation
(NT or TE). In the NT mode, all synchronized signals
are supplied from an external source and the SNIC
uses this timing to transfer
(8/2048) ms
Bit 3
ST-BUS Timing
Channel
Channel 0
Bit 2
30
Bit 5
Bit 1
Channel
31
Bit 0
Channel 0
Bit 4
Channel
0
Application Note
All data is clocked