MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 15

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
4.0 CONTROL INTERFACE PORT
Both
microprocessor port. However, the parallel port on
the MT8930B operates as either a general purpose
microprocessor interface or as a hardwired control/
status port.
4.1
An 8 bit microprocessor port with multiplexed
address and data bus provides a secondary system
interface to the SNIC. Full access is granted to all I/O
channels of the S-Bus or ST-BUS. The data received
on the S-Bus is stored in a temporary register before
being shifted out onto the ST-BUS. It is this register
which is accessed through the microport, thus
explaining the timing restriction on the “synchronous
registers”. The same configuration is used for data
received on the ST-BUS directed to the S-Bus. This
implies that the data will default from S-Bus to ST-
BUS and vice-versa unless the processor intervenes.
The microprocessor also has unique access to the
on-board HDLC formatter.
4.1.1
In microprocessor control mode, the parallel port is
compatible
multiplexed bus signals and timing. The MOTEL
circuit (MOtorola and InTEL compatible bus) on the
A
S
Y
N
C
S
Y
N
C
A4
Microprocessor Port
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
the
Motel Bus
Address Lines
A3
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
MT8930B
with
A2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
either
A1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
and
the
A0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
MT8931B
Motorola
Master Control Register
ST-BUS Control Register
HDLC Control Register 1
HDLC Control Register 2
HDLC Interrupt Mask Register
HDLC Tx FIFO
HDLC Address Byte #1 Register
HDLC Address Byte #2 Register
C-channel Control Register
Control Register 1
Not Available
DSTo C-channel
S-Bus Tx D-channel
DSTo D-channel
S-Bus Tx B1-channel
DSTo B1-channel
S-Bus Tx B2-channel
DSTo B2-channel
Table 5. SNIC Address Map
have
or
Intel
Write
a
SNIC converts the external parallel bus to a
consistent internal time base regardless of the type
of processor being used.
The MOTEL circuit uses the level of the DS/RD pin at
the rising edge of AS/ALE to select the appropriate
bus
AS/ALE then Motorola bus timing is selected.
Conversely, if DS/RD is high at the rising edge of
AS/ALE, then Intel bus timing is selected. This has
the effect of redefining the microprocessor port
transparently to the user.
4.1.2
As mentioned above, the SNIC has multiple registers
which are used to monitor and control the various
functions of the SNIC as well as provide access to
the multiple data channels directed at either the S-
Bus or the ST-BUS ports. These registers are
located in specific address locations as shown in
Table 5. This memory map shows two types of
registers, one being the synchronous access
(registers which are accessible from a serial port)
and the second being the asynchronous access
registers (relevant to the HDLC and Master Control).
4.1.2.1
The synchronous registers have constraints with
respect to the reading and writing to the registers.
timing. If DS/RD is low at the rising edge of
Memory Map
Synchronous Access
verify
verify
verify
HDLC Status Register
HDLC Interrupt Status Register
HDLC Rx FIFO
verify
verify
C-channel Status Register
Not available
Master Status Register
DSTi C-channel
DSTi D-channel
S-Bus Rx D-channel
DSTi B1-channel
S-Bus Rx B1-channel
DSTi B2-channel
S-Bus Rx B2-channel
Read
MSAN-141
A-215