MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 17

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
Note:
In the controllerless mode, the parallel bus has direct
connection to the C-channel control and status
registers for either the TE or NT device. These
control/status pins allow the SNIC to be configured
using a discrete state machine or with manual
switches. All inputs/outputs to the control port will be
latched/refreshed by the SNIC on the falling edge of
the C4b clock midway through the system frame
pulse (F0b). Figure 15 shows the timing diagram
surrounding the structuring of the S- and Q-channels
in the NT controllerless mode.
In the controllerless mode, the SNIC can still be
controlled through the input C-channel on the system
(ST-BUS) interface. The structuring of the serial
control requires the P/SC pin to be tied to V
rendering the remaining control pins as ”don’t cares”.
The option of disabling the ST-BUS channels is not
supported in the controllerless mode, therefore, all
input and output channels will be enabled.
5.0 TRANSMISSION PERFORMANCE
The transmission medium for the subscriber loop is a
four conductor configured as two twisted pairs.
F0b
HALF
MFR
M/S
MCH (NT)
MCH (TE)
Z
2500
265
250
100
as output
Q-Bit
2
M
Q-Bit
Figure 15 - Controllerless Mode Functional Timing
Figure 17 - NT Impedance Template (log-log scale)
S
SS
20
, thus
Frequency (kHz)
Fig. 16 - I-V Characteristics of the Output Driver
To minimize the reflection of a propagating signal, a
100 ohm termination resistor is required in order to
match the characteristic impedance of the twisted
pair cable.
This
transmission line and is thus placed at both ends of
the transmit and receive pair (refer to Figures 7 to 9).
With the TE presenting a high impedance on both
15 mA
I
terminating
Operating Point
Q-Bit
106
M
resistor
0.75
Q-Bit
S
0.95
is
MSAN-141
relevant
1000
20
1.25
1
to
V
A-217
the