PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 285

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
SFCMODE:
SFSMODE:
SFBERTEN:
Z1/S1_CAP:
Reserved:
The SFCMODE alarm bit selects the RASE window size to use for clearing the SF alarm.
When SFCMODE is a logic zero the RASE clears the SF alarm using the same window size
used for declaration. When SFCMODE is a logic one the RASE clears the SF alarm using a
window size that is 8 times longer than the alarm declaration window size. The declaration
window size is determined by the RASE SF Accumulation Period registers.
The SFSMODE bit selects the RASE saturation mode. When SFSMODE is a logic zero
the RASE limits the number of B2 errors accumulated in one frame period to the RASE SF
Saturation Threshold register value. When SFSMODE is a logic one the RASE limits the
number of B2 errors accumulated in one window subtotal accumulation period to the RASE
SF Saturation Threshold register value. Note that the number of frames in a window
subtotal accumulation period is determined by the RASE SF Accumulation Period register
value.
The SFBERTEN bit enables automatic monitoring of line bit error rate threshold events by
the RASE. When SFBERTEN is a logic one, the RASE continuously monitors line BIP
errors over a period defined in the RASE configuration registers. When SFBERTEN is a
logic zero, the RASE BIP accumulation logic is disabled, and the RASE logic is reset to the
declaration monitoring state.
All RASE accumulation period and threshold registers should be set up before SFBERTEN
is written.
The Z1/S1_CAP bit enables the Z1/S1 Capture algorithm. When Z1/S1_CAP is a logic one,
the Z1/S1 clock synchronization status message nibble must have the same value for eight
consecutive frames before writing the new value into the RASE Receive Z1/S1 register.
When Z1/S1_CAP is logic zero, the Z1/S1 nibble value is written directly into the RASE
Receive Z1/S1 register.
The reserved bits must be programmed to logic zero for proper operation.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
285