PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 44

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
9.2
Serial APS Interface Signals
Pin Name
TXD[0]+
TXD[0]-
TXD[1]+
TXD[1]-
TXD[2]+
TXD[2]-
TXD[3]+
TXD[3]-
TXD[4]+
TXD[4]-
TXD[5]+
TXD[5]-
TXD[6]+
TXD[6]-
TXD[7]+
TXD[7]-
REFCLK+
REFCLK-
Pin Name
APECLV
APSI[0]+
APSI[0]-
APSI[1]+
APSI[1]-
APSO[0]+
APSO[0]-
APSO[1]+
APSO[1]-
Type
Differential
Output
Differential
PECL Input
Type
Differential
PECL Input
Differential
PECL
Output
Input
Pin
No.
D2
E2
G2
G1
J2
J1
L2
L3
Y2
Y1
AB1
AB2
AD1
AD2
AF2
AG1
V1
V2
Pin
No.
A17
B17
A18
B18
AK17
AL17
AK18
AL18
AJ18
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Function
The transmit differential data PECL outputs (TXD[7:0]+/)
contain the 155.52 Mbit/s transmit stream. The TXD+/-
outputs are driven using the synthesized clock from the CSU-
622.
The TXD[7:0]+/- are differential TLL outputs which are
converted to PECL levels using external passive networks.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
The differential reference clock inputs (REFCLK+/-) is a 77.76
MHz reference clock for both the clock recovery and the clock
synthesis circuits.
When the WAN Synchronization controller is used,
REFCLK+/- is supplied using a VCXO. In that application, the
serial transmit direction can be externally looped timed to the
line receiver in order to meet wander transfer and holdover
requirements.
Please refer to the Operation section for a discussion of PECL
interfacing issues and reference clocks. For jitter requirement
see Table 30.
Function
The APS PECL signal voltage select (APECLV) selects
between 3.3V PECL signaling and 5V PECL signaling for the
APS (APSI[1:0]+/-) and REFCLK+/- PECL inputs. When
APECLV is low, the APSI[1:0]+/- and REFCLK+/- PECL
inputs expect a 5V PECL signal. When APECLV is high,
these PECL inputs expect a 3.3V PECL signal.
Please refer to the Operation section for a discussion of
PECL interfacing issues.
The receive APS differential data PECL inputs (APSI[1:0]+/-)
contain the NRZ bit serial APS stream for each channel. The
receive clock is recovered from the APS+/- bit stream.
Please refer to the Operation section for a discussion of
PECL interfacing issues and APS functionality.
The transmit APS differential data PECL outputs
(APSO[1:0]+/-) contain the 622.08 Mbit/s transmit APS
stream. The APSO+/- outputs are driven using the
synthesized clock from the clock synthesis unit.
Please refer to the Operation section for a discussion of
PECL interfacing issues and APS functionality.
Released
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