PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 313

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
FOVRI:
CAMI:
TSOCE
TPRTYE:
The FIFO overflow interrupt is set high when a write into the channel FIFO is attempted
while the FIFO is full. Overrunning the FIFO is considered a system error and should not
occur. The FOVRI register bit is cleared immediately after it is read, thus acknowledging
the event has been recorded.
Due to the implemented recovery mechanism from FIFO overflow conditions, overflowing
the TUL3 may cause continuous corrupted ATM cells to be transmitted by the device.
However, resetting the level2 and level3 channel FIFOs will cause the FIFO to heal and
operate properly. This problem occurs on channels configured for ATM cell traffic.
The POS-PHY Level 3 channel address mismatch interrupt is set high when the value of
TDAT[31:24] does not match the associated value of ATM[7:0] or POS[7:0] during in-band
addressing. This interrupt allows the interface to detect when ATM data is being written to
a channel configured for POS traffic or when POS data is being written to a channel
configured for ATM traffic.
When TENB is asserted, TSX assertion is ignored. CAMI may assert when TENB is
asserted and TSX is asserted, indicating that the TSX assertion is being ignored. CAMI will
not assert if a valid channel address exists on the bus when TSX and TENB are both
asserted.
The CAMI register bit is cleared immediately after it is read, thus acknowledging the event
has been recorded.
The start of cell re-alignment interrupt enable controls the assertion of the INTB output
when TSOCI is high. When TSOCE is set high, an interrupt is generated upon assertion
event of the TSOCI register. When TSOCE is set low, changes in the TSOCI status do not
generate an interrupt.
The parity error interrupt enable controls the assertion of the INTB output when TPRTYI is
high. When TPRTYE is set high, an interrupt is generated upon assertion event of the
TPRTYI register. When TPRTYE is set low, changes in the TPRTYI status do not generate
an interrupt.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
313