L9803 STMicroelectronics, L9803 Datasheet - Page 22

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

Clocks, Reset, Interrupts & Power saving modes
Note:
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The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. The value to be stored in the CR register must be
between FFh and C0h (see Table 1):
Table 3.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Figure 9.
The Watchdog delay time is defined by bits 5-0 of the Watchdog register; bit 6 must always
be set in order to avoid generating an immediate reset. Conversely, this can be used to
generate a software reset (bit 7 = 1, bit 6 = 0).
The Watchdog must be reloaded before bit 6 is decremented to “0” to avoid a Reset.
Following a Reset, the Watchdog register will contain 7Fh (bits 0-7).
If the circuit is not used as a Watchdog (i.e. bit 7 is never set), bits 6 to 0 may be used as a
simple 7-bit timer, for instance as a real time clock. Since no reset will be generated under
these conditions, the Watchdog control register must be monitored by software.
–
–
–
f
CPU
WDG Register initial value
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T5:T0 bit contain the number of increments which represents the time delay
before the watchdog produces a reset.
Watchdog Timing (f
Functional Description
WDGA
RESET
FFh
C0h
MSB
WATCHDOG CONTROL REGISTER (WDGCR)
7-BIT DOWNCOUNTER
OSC
WATCHDOG STATUS REGISTER (WDGSR)
CLOCK DIVIDER
÷
= 16 MHz)
12288
WDG timeout period (ms)
LSB
98.3
1.54
WDGF
L9803