L9803 STMicroelectronics, L9803 Datasheet - Page 53

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
Note:
5.2.4
1
2
3
4
5
t
f
The Output Compare 2 event causes the counter to be initialized to FFFCh (See
on page
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can
be set and IC2R can be loaded) but the user must take care that the counter is reset after
each period and ICF1 can also generate an interrupt if ICIE is set.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 28. Pulse Width Modulation Mode Timing
Register Description
Each Timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Timer1 Register Address: 0032h
Timer2 Register Address: 0042h
Read/Write
Reset Value: 0000 0000(00h)
EXT
ICIE
7
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
COUNTER
OCMP1
53).
Note: OCR1=2ED0h, OCR2=34E2, OLVL1=0, OLVL2= 1
OCIE
compare2
34E2
TOIE
FFFC FFFD FFFE
FOLV2
OLVL2
FOLV1
compare1
2ED0 2ED1 2ED2
OLVL2
OLVL1
On-Chip Peripherals
IEDG1
compare2
34E2
OLVL2
Figure 28
FFFC
OLVL1
0
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