L9803 STMicroelectronics, L9803 Datasheet - Page 50

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L9803

Manufacturer Part Number
L9803
Description
Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
Manufacturer
STMicroelectronics
Datasheet

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One Pulse Mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The One Pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use One Pulse mode:
1.
2.
3.
.
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2
bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the
IC1R register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1.
2.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the section).
Select the following in the CR1 register:
Select the following in the CR2 register:
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
Set the OPM bit.
Select the timer clock CC[1:0] (see
OCiR Value
event occurs
on ICAP1
Counter
= OCR1
When
When
One pulse mode cycle
Table 9: Clock Control
=
OCMP1 = OLVL2
Counter is reset
OCMP1 = OLVL1
--------------------- - 5
PRESC
ICF1 bit is set
t f
to FFFCh
CPU
Bits).
L9803

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