L9803 STMicroelectronics, L9803 Datasheet - Page 42

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

On-Chip Peripherals
5.2.2
Note:
5.2.3
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Main Features
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The Block Diagram is shown in
Some external pins are not available on all devices. Refer to the device pin out description.
Functional Description
Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high & low.
Counter Register (CR):
Alternate Counter Register (ACR)
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register (SR). (See note at the end of paragraph titled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.
Programmable prescaler: f
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
Output compare functions with
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Input capture functions with
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Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports
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2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
Counter High Register (CHR) is the most significant byte (MS Byte).
Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter High Register (ACHR) is the most significant byte (MS Byte).
Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte).
cpu
Figure 19 on page
divided by 2, 4 or 8.
43.
L9803