L9803 STMicroelectronics, L9803 Datasheet - Page 78

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

On-Chip Peripherals
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Figure 39. CAN Controller State Diagram
n
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RUN bit being read-back as 0.
Once in standby, the only event monitored is the reception of a dominant bit which
causes a wake-up interrupt if the SCIE bit of the Interrupt Control Register (ICR) is set.
The STANDBY mode is left by setting the RUN bit. If the WKPS bit is set in the CSR
register, then the controller passes through WAKE-UP otherwise it enters RESYNC
directly.
It is important to note that the wake-up mechanism is software-driven and therefore
carries a significant time overhead. All messages received after the wake-up bit and
before the controller is set to run and has completed synchronization are ignored.
WAKE-UP. The CAN bus line is forced to dominant for one bit time signalling the wake-
up condition to all other bus members.
RESYNC. The resynchronization mode is used to find the correct entry point for
starting transmission or reception after the node has gone asynchronous either by
going into the STANDBY or bus-off states.
Resynchronization is achieved when 128 sequences of 11 recessive bits have been
Write to DATA7 |
TX Error & NRTX
TRANSMISSION
TX Error
RUN
RUN
TX OK
Arbitration lost
STANDBY
RESYNC
ARESET
ERROR
IDLE
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF) & 128 * 11 Recessive bits
RX OK
RUN & WKPS
RUN & WKPS
BOFF
BOFF
RECEPTION
Start Of Frame
RX Error
WAKE-UP
L9803