ST92185B STMicroelectronics, ST92185B Datasheet - Page 136
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ST92185B
Manufacturer Part Number
ST92185B
Description
16k/24k/32k Rom Hcmos Mcu With On-screen-display
Manufacturer
STMicroelectronics
Datasheet
1.ST92185B.pdf
(178 pages)
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ST92185B - SYNC CONTROLLER
7.5 SYNC CONTROLLER
The SYNC Controller receives Horizontal / Vertical
sync information coming from the chassis. The
VSYNC and HSYNC inputs use schmitt triggers to
guarantee sufficient noise rejection.
The SYNC Controller unit provides the H internal
sync signal to the Display Skew Corrector, which
rephases the Pixel clock.
It provides also the H and V internal sync signals
to the TDSRAM Controller to perform correct TV
line counting, thus generating the necessary time
windows for a proper TDSRAM access real time
Figure 83. Sync Controller Block Diagram
n
136/178
VSYNC
HSYNC
CSYNC
(from Sync Ext.)
VPOL
Field
MOD1
MOD0
4 MHz
VPOL
SCCS0 Register
HPOL
HPOL
VSEP
VPOL
VDLY
1
0
HSF(3:0)
H generator
Internal
(64 µs)
Sync Extr.
MOD0
Vertical
MOD1
VDLY
MOD0
1
0
FLDEV
SCCS1R Register
MOD1
Vertical Pulse
Generator
FLDST
Hpls
Hpls
VSEP
EOFVBI
Composite Sync.
& Line Sequencer
FSTEN
Equalization Pulse
Generator
sharing by the Display Controller and the CPU (for
more details refer to the TDSRAM Controller chap-
ter). Field information is also available for the Dis-
play Controller.
The SYNC Controller unit also generates two in-
terrupt sources corresponding respectively the TV
field start and to the end of VBI event (“VBI” stands
for Vertical Blank Interval).
The SYNC Controller implements also a “Compos-
ite Sync” signal generator which provides a com-
posite sync output signal (called CSO) available
through an I/O port alternate function.
VBIEN
Controller
Vertical
Hint
HFLG
Pulse
shaper
HSF(3:0)
(MOD0+MOD1)*VSEP
pgmble
delay
Pulse
shaper
Vcso
line counter
Hout
(to DISPLAY, etc.)
Vout
Vout
FLDST
interrupt
Field
detect.
(to DISPLAY, etc.)
CSO_AF
Vout
VR02092A
interrupt
EOFVBI
FLDEV