ST92185B STMicroelectronics, ST92185B Datasheet - Page 151

• Manufacturer Part Number: ST92185B
• Description: 16k/24k/32k Rom Hcmos Mcu With On-screen-display
• Manufacturer: STMicroelectronics

SERIAL PERIPHERAL INTERFACE (Cont’d)
Bit 2 = CPHA: Transmission Clock Phase.
CPHA controls the relationship between the data
on the SDI and SDO pins, and the clock signal on
the SCK pin. The CPHA bit selects the clock edge
used to capture data. It has its greatest impact on
the first bit transmitted (MSB), because it does (or
does not) allow a clock transition before the first
data capture edge.
ship between CPHA, CPOL and SCK, and indi-
cates active clock edges and strobe times.
Figure 96. SPI Data and Clock Timing
CPOL
0
0
1
1
CPHA
0
1
0
1
Figure 11
(in
shows the relation-
Figure
SCK
(a)
(b)
(c)
(d)
11)
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
Bit 1:0 = SPR[1:0]: SPI Rate.
These two bits select one (of four) baud rates, to
be used as SCK.
SPR1 SPR0
0
0
1
1
0
1
0
1
Divider
Clock
128
256
16
8
3000kHz
1500kHz
187.5kHz
93.75kHz
(@ INTCLK = 24MHz)
SCK Frequency
(T = 0.33 s)
(T = 0.67 s)
(T = 5.33 s)
(T = 10.66 s)
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