ST92185B STMicroelectronics, ST92185B Datasheet - Page 63
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ST92185B
Manufacturer Part Number
ST92185B
Description
16k/24k/32k Rom Hcmos Mcu With On-screen-display
Manufacturer
STMicroelectronics
Datasheet
1.ST92185B.pdf
(178 pages)
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FREQUENCY MULTIPLIERS (Cont’d)
For the Off-chip filter components please refer to
the Required External Components figure provid-
ed in the first section of the data sheet.
The frequency multipliers are off during and upon
exiting from the reset phase. The user must pro-
gram the desired multiplying factor, start the multi-
plier and then wait for its stability.
Once the Core/Peripherals multiplier is stabilized,
the Main Clock controller can be re-programmed
(through the FMSL bit, MCCR.6) to provide the fi-
nal frequency (INTCLK) to the CPU.
The
switched off when the µP enters in HALT mode
(the HALT mode forces the control register to its
reset status).
Table 10. Examples of CPU speed choice
Table 12. External PLL Filter Stabilisation time
Clock Pin Name
Frequency
Crystal
4 MHz
frequency
MCFM
PXFM
multipliers
FML
(3:0)
4
Main Clock PLL Filter Input Pin
Pixel Clock PLL Filter Input Pin
Internal Frequency
are
Clock Name
10 MHz
(Fimf)
automatically
ST92185B - TIMING AND CLOCK CONTROLLER
Note: 24 MHz is the max. CPU authorized frequency.
Table 11. DOTCK/2 frequency choices
(*) Preferred values for 4/3.
(**) 16/9 screen formats.
Note: 18 MHz is the min. DOTCK/2 authorized frequency.
Control Register
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
SKW
(3:0)
PXCCR
10
11
MCCR
8
9
11
5
6
7
8
Stabilization Period
35 ms.
24 MHz (**)
35 ms
20 MHz(*)
DOTCK/2
18 MHz
22 MHz
12 MHz
14 MHz
16 MHz
18 MHz
24 MHz
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