ST92185B STMicroelectronics, ST92185B Datasheet - Page 9

• Manufacturer Part Number: ST92185B
• Description: 16k/24k/32k Rom Hcmos Mcu With On-screen-display
• Manufacturer: STMicroelectronics

1.2 PIN DESCRIPTION
RESET Reset (input, active low). The ST9+ is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue . Video color analog DAC
outputs.
FB Fast Blanking . Video analog DAC output.
V
V
gramming voltage pin. V
in user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
Figure 2. 56-Pin Package Pin-Out
DD
PP
: On EPROM/OTP devices, V
Main power supply voltage (5V±10%, digital)
PP
CSO/RESET0/P3.7
should be tied to GND
SCK/INT2/P5.0
SDI/SDO/P5.1
AIN4/P0.2
INT7/P2.0
PP
RESET
AVDD3
TEST0
MCFM
JTDO
JTCK
P0.7
P0.6
P0.5
P0.4
P0.3
P0.1
P0.0
P3.6
P3.5
P3.4
V
V
N.C
is the pro-
FB
DD
PP
G
R
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSYNC Vertical Sync . Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
HSYNC/CSYNC Horizontal/Composite sync . Hori-
zontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3 Analog V
to V
GND Digital circuit ground.
AGND Analog circuit ground (must be tied exter-
nally to digital GND).
AVDD1, AVDD2 Analog power supplies (must be
tied externally to V
CVBSO, JTDO, JTCK, JTMS Test pins: leave
floating.
TEST0 Test pin: must be tied to AVDD2.
JTRST0 Test pin: must be tied to GND.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
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DD
ST92185B - GENERAL DESCRIPTION
N.C
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
N.C
N.C
JTMS
AVDD2
CVBSO
externally.
DD
DD
of PLL. This pin must be tied
).
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