ST92185B STMicroelectronics, ST92185B Datasheet - Page 152

• Manufacturer Part Number: ST92185B
• Description: 16k/24k/32k Rom Hcmos Mcu With On-screen-display
• Manufacturer: STMicroelectronics

ST92185B - A/D CONVERTER (A/D)
7.7 A/D CONVERTER (A/D)
7.7.1 Introduction
The 8 bit Analog to Digital Converter uses a fully
differential analog configuration for the best noise
immunity and precision performance. The analog
voltage references of the converter are connected
to the internal AV
the chip if they are available, otherwise to the ordi-
nary V
guaranteed accuracy depends on the device (see
Electrical Characteristics). A fast Sample/Hold al-
lows quick signal sampling for minimum warping
effect and conversion error.
7.7.2 Main Features
Figure 97. A/D Converter Block Diagram
n
152/178
– 138 internal system clock periods in slow
– 78 INTCLK periods in fast mode (~6.5 µs @
– 84 INTCLK periods in slow mode (~3.4 µs
– 48 INTCLK periods in fast mode (~4 µs
8-bit resolution A/D Converter
Single Conversion Time (including Sampling
Time):
Sample/Hold: Tsample=
Up to 4 Analog Inputs (the number of inputs is
device dependent, see device pinout)
mode (~5.6 µs @25Mhz internal system
clock);
12MHZ internal system clock)
@25Mhz internal system clock)
@12Mhz internal system clock)
DD
and V
SS
DD
supply pins of the chip. The
& AV
REGISTER
DATA
SS
analog supply pins of
APPROXIMATION
SUCCESSIVE
REGISTER
CONTROL LOGIC
S/H
7.7.3 General Description
Depending on the device, up to 8 analog inputs
can be selected by software.
Different conversion modes are provided: single,
continuous, or triggered. The continuous mode
performs a continuous conversion flow of the se-
lected channel, while in the single mode the se-
lected channel is converted once and then the log-
ic waits for a new hardware or software restart.
A data register (ADDTR) is available, mapped in
page 62, allowing data storage (in single or contin-
uous mode).
The start conversion event can be managed by
software, writing the START/STOP bit of the Con-
trol Logic Register or by hardware using either:
– An external signal on the EXTRG triggered input
– An On Chip Event generated by another periph-
(negative edge sensitive) connected as an Alter-
nate Function to an I/O port bit
eral, such as the MFT (Multifunction Timer).
Single/Continuous Conversion Mode
External/Internal
synchronization)
Power Down mode (Zero Power Consumption)
1 Control Logic Register
1 Data Register
ANALOG
(On Chip Event)
MUX
INTRG
source
Trigger
EXTRG
Ain0
Ain1
Ainx
(Alternate