HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 11

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

2.5
2.6
u)
2.7
(e. g. for PCM codecs)
2.8
The external EEPROM is optional. EE_SCL/EN must be connected to GND if no external EEPROM is
available.
u)
6URbeQbi !)))
Pin No.
51
50
54
55
56
57
58
59
63
62
internal pull up
internal pull up
Oscillator
GCI/IOM2 bus interface
GCI/IOM2 Timeslot enable signals
EEPROM interface
OSC_IN
OSC_OUT
C4IO
F0IO
STIO1
STIO2
F1_A
F1_B
EE_SDA
EE_SCL/EN
Pin Name
Output
Input
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
u)
u)
u)
u)
u)
u)
Function
Oscillator input or quarz connection 12.288 MHz
Oscillator output or quarz connection
4.096 MHz clock
GCI/IOM2 bus clock master: output
GCI/IOM2 bus clock slave: input (reset default)
Frame synchronisation, 8kHz pulse for GCI/IOM2 bus frame
synchronisation
GCI/IOM2 bus master: output
GCI/IOM2 bus slave: input (reset default)
GCI/IOM2 bus databus I
Slotwise programmable as input or output
GCI/IOM2 bus databus II
Slotwise programmable as input or output
enable signal for external CODEC A
Programmable as positive (reset default) or negative pulse.
enable signal for external CODEC B
Programmable as positive (reset default) or negative pulse.
Serial data of external EEPROM
Clock of external EEPROM / EEPROM enable
!! _V &$