HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 27

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

Figure 6: FIFO Data Organisation
The ending flag of a HDLC-frame can also be the starting flag of the next frame.
After a frame is received completely F1 is incremented by the HFC-S PCI automatically and the next
frame can be received.
After reading a frame via the host bus interface F2 must be incremented. If the frame counter F2 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are
Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 5).
Z1(F1) is used for the frame which is just received from the S/T device side of the HFC. Z2(F2) is used
for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of frame pointer
of the current output frame.
To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1.
In the receive channels F2 must be incremented to point to the next Z1/Z2 pair. If Z1 = Z2 and F1 = F2
the FIFO is totally empty.
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