HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 19

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HFC-SPCI

Manufacturer Part Number
HFC-SPCI
Description
Isdn S/t HDLC Basic Rate Controller
Manufacturer
Cologne Chip AG
Datasheet
3.2.2
GCI/IOM2 bus timeslot selection registers
GCI/IOM2 bus timeslot selection registers
GCI/IOM2 bus data registers
6URbeQbi !)))
CIP / I/O-address
0000 1000
0000 1100
0010 1000
0010 1100
CIP / I/O-address
1000 0000
1000 0100
1000 1000
1000 1100
1001 0000
1001 0100
1001 1000
1001 1100
CIP / I/O-address
1010 0000
1010 0100
1010 1000
1010 1100
*)
Registers of the GCI/IOM2 bus section
These registers are read/written automatically by the HDLC FIFO controller (HFC) or by the
S/T controller and need not be accessed by the user.
08h
0Ch
28h
2Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
Name
C/I
TRxR
MON1_D
MON2_D
Name
B1_SSL
B2_SSL
AUX1_SSL
AUX2_SSL
B1_RSL
B2_RSL
AUX1_RSL
AUX2_RSL
Name
B1_D
B2_D
AUX1_D
AUX2_D
*)
*)
r/w
r/w
r
r/w
r/w
r/w
w
w
w
w
w
w
w
w
r/w
r/w
r/w
r/w
r/w
Function
C/I command/indication register
Monitor Tx ready handshake
first monitor byte
second monitor byte
Function
B1-channel transmit slot (0..31)
B2-channel transmit slot (0..31)
AUX1-channel transmit slot (0..31)
AUX2-channel transmit slot (0..31)
B1-channel receive slot (0..31)
B2-channel receive slot (0..31)
AUX1-channel receive slot (0..31)
AUX2-channel receive slot (0..31)
Function
GCI/IOM2 bus B1-channel data register
GCI/IOM2 bus B2-channel data register
AUX1-channel data register
AUX2-channel data register
!) _V &$

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