HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 12

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

2.9
2.10
The reset signal (hardware reset or software reset) must be active for at least 4 clock cycles.
The GCI/IOM2 bus lines STIO1, STIO2 and the interrupt lines are in tristate mode after a reset.
The HFC-S PCI is in slave mode after reset. C4IO and F0IO are inputs.
The S/T state machine is stuck to '0' after reset. This means the HFC-S PCI does not react to any signal
on the S/T interface before the S/T state machine is initialised.
The registers' initial values are described in the Register bit description (section 4 of this data sheet).
During initialisation phase the HFC-S PCI must not be accessed. Bit 1 of the STATUS register is cleared
to '0' to indicate that the initialisation phase has been finished.
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7, 28, 48, 60, 76, 89
8, 17, 29, 39, 49, 52, 61, 64, 77,
83, 90, 96
*
All power supply pins VDD must be directly connected to each other. Also all pins GND must be
directly connected to each other.
To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be
placed between each pair of VDD/GND pins.
important!
Power supply
RESET characteristics
Pin No.
VDD
GND
Pin Name
Function
VDD (+3.3V or +5V)
GND
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