HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 60

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

10.2
Clock synchronisation in TE-mode
Figure 17: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus twice for one half clock cycle. This
can be reduced to one adjustment of a half clock cycle. This is useful if another HFC-S, HFC-S+, HFC-
SP or HFC-S PCI is connected as slave in NT mode to the GCI/IOM2 bus.
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