HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 38

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

#( _V &$
Name
CTMT
CHIP_ID
B_MODE
Addr.
4Ch
64h
58h
Bits
4..2
3..1
7..4
1..0
0
1
5
6
7
0
2
3
4
5
6
7
r/w Function
w
w
w
w
w
w
w
w
w
w
w
w
w
r
r
r
'0' HDLC mode (reset default)
'1' transparent mode
HDLC/transparent mode for B2-channel
'0' HDLC mode (reset default)
'1' transparent mode
'000'
'001'
'010'
'011'
'100'
'101'
'110'
'111'
timer reset mode
'0' reset timer by CTMT bit 7 (reset default)
'1' automatically reset timer at each access to HFC-S PCI
ignored
reset timer
'1' reset timer
This bit is automatically cleared.
'0' 5V PCI signaling environment
'1' 3.3V PCI signaling environment
reserved
0011b
unused
in 64 kbit/s mode: bit is ignored
in 56 kbit/s mode: value of the LSB in 7-bit mode
unused
56 kbit/s mode selection bit for B1-channel
'0' 64 kbit/s mode (reset default)
'1' 56 kbit/s mode
56 kbit/s mode selection bit for B2-channel
'0' 64 kbit/s mode (reset default)
'1' 56 kbit/s mode
'0' Data not inverted for B1-channel (reset default)
'1' Data inverted for B1-channel
'0' Data not inverted for B2-channel (reset default)
'1' Data inverted for B2-channel
HDLC/transparent mode for B1-channel
select timer (bit 4 = MSB)
power supply
Chip identification
timer
off
3.125ms
6.25ms
12.5ms
25ms
50ms
400ms
800ms
HFC-S PCI
6URbeQbi !)))