HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 25

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.4.3
FIFO channel operation
Figure 5: FIFO Organisation (shown for B-channel, similar for D-channel)
3.4.3.1 Send channels (B1, B2 and D transmit)
The send channels send data from the host bus interface to the FIFO and the HFC-S PCI converts the
data into HDLC code and tranfers it from the FIFO into the S/T or/and the GCI/IOM2 bus interface write
registers.
The HFC-S PCI checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-S PCI generates a HDLC-Flag
(01111110) and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC
flags are sent to the S/T interface and all counters remain unchanged. If the frame counters are unequal
F2 is incremented and the HFC-S PCI tries to send the next frame to the output device. After the end of a
frame (Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If
there is another frame in the FIFO (F1 F2) the F2 counter is incremented.
With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a
complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are
Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 5).
Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame
which is just beeing transmitted to the S/T device side of the HFC-S PCI. Z1(F2) is the end of frame
pointer of the current output frame.
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