HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 3

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

Contents
1 General description.................................................................................................................................. 6
1.1 Applications ............................................................................................................................................ 7
2 Pin description.......................................................................................................................................... 8
2.1 PCI bus interface..................................................................................................................................... 8
2.2 Auxiliary port........................................................................................................................................ 10
2.3 S/T interface transmit signals ............................................................................................................... 10
2.4 S/T interface receive signals ................................................................................................................. 10
2.5 Oscillator............................................................................................................................................... 11
2.6 GCI/IOM2 bus interface ....................................................................................................................... 11
2.7 GCI/IOM2 Timeslot enable signals ...................................................................................................... 11
2.8 EEPROM interface ............................................................................................................................... 11
2.9 Power supply......................................................................................................................................... 12
2.10 RESET characteristics ........................................................................................................................ 12
3 Functional description........................................................................................................................... 13
3.1 PCI-interface ......................................................................................................................................... 13
3.2 Internal HFC-S PCI register description............................................................................................... 17
3.3 Timer..................................................................................................................................................... 21
3.4 FIFOs .................................................................................................................................................... 22
4 Register bit description ......................................................................................................................... 30
4.1 Register bit description of S/T section ................................................................................................. 30
4.2 Register bit description of GCI/IOM2 bus section ............................................................................... 33
4.3 Register bit description of CONNECT register.................................................................................... 36
4.4 Register bit description of auxiliary and cross data registers ............................................................... 37
5 Electrical characteristics ....................................................................................................................... 42
6 Timing characteristics ........................................................................................................................... 46
6.1 PCI bus timing ...................................................................................................................................... 46
6.2 GCI/IOM2 bus clock and data alignment for Mitel ST
6.3 GCI/IOM2 timing.................................................................................................................................. 47
6.4 EEPROM access ................................................................................................................................... 48
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3.1.1 PCI access types used by HFC-S PCI............................................................................................ 13
3.1.2 PCI modes supported..................................................................................................................... 13
3.1.3 PCI buffer signaling and power supply environment .................................................................... 13
3.1.4 PCI configuration registers............................................................................................................ 14
3.2.1 Registers of the S/T section........................................................................................................... 18
3.2.2 Registers of the GCI/IOM2 bus section ........................................................................................ 19
3.2.3 Interrupt and status registers.......................................................................................................... 20
3.4.1 FIFO counters location in Memory Window ................................................................................ 23
3.4.2 FIFO data location in Memory Window ....................................................................................... 24
3.4.3 FIFO channel operation ................................................................................................................. 25
3.4.4 Transparent mode of HFC-S PCI .................................................................................................. 29
3.4.3.1 Send channels (B1, B2 and D transmit) ................................................................................. 25
3.4.3.2 Automatically D-channel frame repetition............................................................................. 26
3.4.3.3 FIFO full condition in send channels ..................................................................................... 26
3.4.3.4 Receive Channels (B1, B2 and D receive)............................................................................. 26
3.4.3.5 FIFO full condition in receive channels................................................................................. 28
3.4.3.6 FIFO initialisation .................................................................................................................. 28
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bus.............................................................. 46
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