W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 11

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

GPIO[12]
GPIO[13:14]
GNT2#/
nAutoFd
GNT3#/
NStrobe
REQ2#/
NAck
REQ3#/
Busy
INTD#/
WGLBCS#
PDA[31:24]/
WA[23:16]/
WD[15:8]
PDA[23:8]/
WA[15:0]
PDA[7:0]/
WD[7:0]
C/BE3#/
WIOCS#
C/BE2#/
WROMCS#
C/BE1#/
WWR#
C/BE0#/
WRD#
W90221X version 0.6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
82, 80-77, 63-
61, 59-57, 50,
100-98, 94,
85, 84, 83,
93, 90-88
136, 137
45-38
151
153
154
155
156
32
49
87
76
65
47
PCI/WIO Bus Bridge
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP "nFault" (input).
If parallel port is not enabled (port 0x3e[4:5] = 00), this pin
provides general purpose I/O function (In/Out).
During "clock test" mode (port 0x3e[4] = 01), this pin outputs
internal MCLK_DATA (output).
These two pins always provide general purpose I/O function.
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP "nAutoFd".
If parallel port is not enabled (port 0x3e[4:5] = 0x), this pin
outputs PCI bridge Grant Two "GNT2#".
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP "nStrobe".
If parallel port is not enabled (port 0x3e[4:5] = 0x), this pin
outputs PCI bridge Grant Three "GNT3#".
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP "nAck".
If parallel port is not enabled (port 0x3e[4:5] = 0x), this pin
inputs master Request Two "REQ2#".
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP "Busy".
If parallel port is not enabled (port 0x3e[4:5] = 0x), this pin
inputs master Request Three "REQ3#".
During PCI cycles: If WIO is enabled, this signal shall not
connect to any PCI bus master.
During WIO cycles: Asserted low indicating a WIO command
cycle is ongoing
During PCI cycles: These pins serve as the highest byte of
PCI 32-bit address/data bus.
During WIO memory cycles0: These pins serve as the
highest byte of 24-bit address lines (XA[8:31])
During WIO IO cycles: These pins serve as the high byte of
16-bit data lines (XD[15:0]).
During PCI cycles: These pins serve as bits 16-31 of PCI 32-
bit address/data bus.
During WIO cycles: These pins serve as the lower 16-bit of
24-bit address lines (XA[8:31]).
During PCI cycles: These pins serve as the lowest byte of
PCI 32-bit address/data bus.
During WIO memory cycles: These pins serve as the 8-bit
data lines.
During WIO IO cycles: These pins serve as the low byte of
16-bit data lines (XD[15:0]).
During PCI cycles: Bit-3 of Command/Byte Enable bus
During WIO cycles: WIO chip-select for its IO devices
During PCI cycles: Bit-2 of Command/Byte Enable bus
During WIO cycles: WIO chip-select for its memory devices
During PCI cycles: Bit-1 of Command/Byte Enable bus
During WIO cycles: Asserted low, if WGLBCS# is low also,
indicating that a WIO write command cycle is ongoing
During PCI cycles: Bit-0 of Command/Byte Enable bus
During WIO cycles: Asserted low, if WGLBCS# is low also,
indicating that a WIO read command cycle is ongoing
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