W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 188

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

boundary automatically. (ie,
of their relative base
AIR[4] : NonCacheable Base register
2
AIR[5] : reserved
AIR[6] : reserved
AIR[7] : (HPSW[0:31])
AIR[8] : (ICEA_Front, ICEA_Back)
AIR[9] : (IDR[0:31]) ICE-Data register
AIR[10] : (ITR[0:31]) ICE-Trap register
AIR[11] : (PWR[0:2]) Power-Mode register
AIR[12] : (CKR[0:7]) Stand-By-Clock register
W90221X version 0.6
- bit 27-29: reserved
- bit 30
- bit 31
- bit 0-15 : base address of non-cacheable region 1
- bit 16-31
- bit 0
- bit 1
- bit 2
STDCLK = CPUCLK /((CKR[0:7]+1)*4)
Define the clock rate (STDCLK) in Stand-By mode :
This register defines which trap event would force pipeline enter HALT state.
Back up states of PSW as pipeline enter HALT state.
This register is used for data exchange between ICE module and CPU.
Back up IAOQ_Frond and IAOQ_Back as pipeline enter HALT state
: Data cache write-through mode
: reserved
: (SLEEP) Force CPU into sleep mode
: (DOZE) Force CPU to doze-mode
: (STDBY) Force CPU to stand-by-mode
0 : write-back data cache
1 : write-through data cache
cacheable base register (AIR[4]), will be on each regions'
according to the size of each non-cacheable region, some LSBs
register will be neglected.
(default : 32'b0)
: base address of non-cacheable region
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