W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 39

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W90221X

Manufacturer Part Number
W90221X
Description
Pa-risc Embedded Controller
Manufacturer
Winbond Electronics Corp America
Datasheet
5.13 Synchronous Serial interface (SSI)
5.13.1 Overview
The SSI module within W90221X contains holding registers, shift registers, and other logic to
support a variety of serial data communications protocols and provide a direct connection to
external audio/telephony codec devices. Two 48-half-word FIFOs, one transmitter FIFO and
one receiver FIFO, have been implemented to accelerate both transmitting and receiving
operations. These two FIFOs can be configured as 48 half-word or 24 words depth depending
on the data word length.
5.13.2 Block Diagram
Figure 5.13.2.1 Block diagram of SSI
5.13.3 Features
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5.13.4 Related Pins
SDI (input)
SDO (output)
SYNC (in/out)
W90221X version 0.6
Supports "long framing" and "short framing" (synchronous, frame-based protocol)
Provides "master mode" and "slave mode"
Build-in two 48x16 (or 24x32) data FIFOs accelerating transmit/receive operation
Programmable data bits per one frame (sampling rate) : 1 ~ 256 bits/frame
Programmable data bits per word (resolution of each sampling) : 1 ~ 32 bits/word
Programmable multi-word (per frame) transfer : 1 ~ 16 words/frame
This pin contains the input data shifted from external audio/telephony codec devices.
This pin contains the output data shifted to external audio/telephony codec devices.
This pin is the frame synchronization signal between SSI and codec devices. The SYNC
may be input or output depending on SSI operated in slave- or master-mode
respectively.
LSR[1] will indicate that both TX-FIFO and shift register are empty.
LSR[0] will indicate whether there are any errors in the RX-FIFO.
SDO
32-bit TX-Shift reg
(48x16/24x32)
TX-FIFO
16/32
16/32
32-bit CPU bus
SYNC SCLK
& Shift-in/out
SCLK/SYNC
FIFO Control
control
Logic
32-bit RX-Shift reg
(48x16/24x32)
RX-FIFO
16/32
16/32
SDI
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