W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 21

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W90221X

Manufacturer Part Number
W90221X
Description
Pa-risc Embedded Controller
Manufacturer
Winbond Electronics Corp America
Datasheet
Note : cfg = bit[4:5] of port 0xf000003e
5.5.4 Operation Modes
The following figure shows PIO timing diagram for the input pin data -- the shortest time, the
pio interrupt register will generate an interrupt and will latch the pin input data into the input
data register.
Figure 5.5.4.1 Shortest PIN_DATA should be kept to generate interrupt and latch the
input data to PIO.
The following figure shows PIO timing diagram for the input pin data -- the longest time, the
PIO interrupt register will not generate an interrupt and will not latch the pin input data into the
input data register.
Figure 5.5.4.2 Longest PIN_DATA will not generate interrupt and will not latch the input
data to PIO.
W90221X version 0.6
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[9]
PIN_DATA
TSCK_BUN
PIN_DATA
TSCK_BUN
PIN_REG
PIN_REG
PINT
PINT
GNT2# (out)
GNT3# (out)
PIO[10] (io)
PIO[11] (io)
PIO[12] (io)
PIO[13] (io)
PIO[14] (io)
REQ2# (In)
REQ3# (In)
PIO[9] (io)
0.7ns
0.7ns
1.5ns
MCLK_DATA (out)
MCLK_CTL (out)
CPUCLK (out)
GNT2# (out)
GNT3# (out)
PIO[13] (io)
PIO[14] (io)
REQ2# (In)
REQ3# (In)
PIO[9] (io)
0.3ns
nSelectIn (out)
nAutoFd (out)
nStrobe (out)
PIO[13] (io)
PIO[14] (io)
PError (In)
Select (In)
nFault (In)
nAck (In)
Busy (In)
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