W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 61

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

DRAM Timing Control Register 2 (DRAMTCTL2)
Port address: 0x0000003e
Bits 0-1
Bits 2-3
Bit 4
Bit 5
Bits 6-8
W90221X version 0.6
CLKDC[2]
LDI2PRE[0:1]
0
8
1
9
MCLK_OUT_SEL [0:2]
Last data-in to precharge command during write cycle
MCLK frequency select
ECP enable
When this bit is set, the GPIO[0:12] and GPIO[15:18] are redefined as
parallel port interface.
Test mode for outputting CPUCLK, MCLK_CTL, and MCLK_DATA
When this bit is set and bit-4 is reset, the above three internal clocks
are showed on pins GPIO[10:12]. This mode is used to adjust phase
skew of MCLK.
MCLK output buffer control
DRAMTCTL2
DRAMTCTL2
DRAMTCTL2
MCLK Freq. Select
10
2
[0:1]
[2:3]
[6:8]
000
00
01
10
11
00
01
10
11
Access type: read/write
11
3
Capacity (mA)
MCLK Driving
Time (MCLK)
CAS# Active
CPUCLK/1.5
MCLK Freq.
CPUCLK/2
Reserved
CPUCLK
Select
PRE_ALL
16
ENECP
1
2
3
4
12
4
TEST
13
5
Reserved
14
6
CLKDC[0:1]
Default: 0x0
15
7
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