W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 166

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

Bit 3 Break Interrupt indicator
Bit 4 Framing Error indicator
Bit 5 Parity Error indicator
Bit 6 Overrun Error indicator
Bit 7 RX FIFO Data Ready
LSR[3:5] (BI, FE, PE) is revealed to the CPU when its associated character is
at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the
contents of the LSR.
LSR[3:6] (BI, FE, PE, OE) are the error conditions that produce a "receiver
line status interrupt"
(Irpt_RLS) when IER[5]=1. Read LSR clear Irpt_RLS.
Writing LSR is a null operation (not suggested).
W90221X version 0.6
UART to issue an interrupt (Irpt_THRE) to the CPU when IER[6]=1.
This bit is set to a logic 1 whenever the received data input is held in
the "spacing state"
(logic 0) for longer than a full word transmission time (that is, the
total time of "start bit"
+ data bits + parity + stop bits).
This bit is set to a logic 1 whenever the received character did not
have a valid "stop bit"
(that is, the stop bit following the last data bit or parity bit is detected
as a logic 0).
This bit is set to a logic 1 whenever the received character did not
have a valid "parity bit".
An overrun error will occur only after the RX FIFO is full and the next
character has been
completely received in the shift register. The ccharacter in the shift
register is overwritten,
but it is not transferred to the RX FIFO. OE is indicated to the CPU
as soon as it happens
and is reset whenever the CPU reads the contents of the LSR.
0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
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