W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 40

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

SCLK (in/out)
5.13.5 Operations Modes
Master Mode
Slave Mode
Loop mode
Long Framing
W90221X version 0.6
This pin is the serial bit clock between SSI and codec devices. Likewise, The SCLK may
be input or output depending on SSI operated in slave- or master-mode respectively.
Once CFGH[2] is set to logic 1 and MD[25] is pull high, SSI is operated in master mode,
and the SYNC (determines the sampling rate) and SCLK are drove by SSI module to
external CODEC devices.
Once CFGH[2] is set to logic 0 and MD[25] is pull down, SSI is operated in slave mode,
the SCLK and SYNC are drove externally (may be from CODEC devices). So the
sampling rate and SCLK frequency are determined by external devices, however
software driver still need to properly set "serial data bit length" (CFGH[8:10] ) as well as
"data words per frame" ( CFGH[12:15] ) to make SSI module working correctly.
This mode (CFGH[1] =1) aims at self-testing. When this bit is set, serial data-out "SDO"
is connected to serial data-in "SDI" internally and SDO pin fixed at logic 0 state. Besides,
if Loop and Master mode are chosen concurrently, SSI module will not issue SYNC
until TX-FIFO contains at least one data word.
When CFGH[3] is set to logic 1, SSI is operated in long framing mode. The following
features are included in long framing mode:
The SSI module always samples receive date (SDI) on the falling edge of SCLK,
whereas always pushes transmit data (SDO) on the rising edge of SCLK.
The frame sync (SYNC) is asserted immediately as the first bit of transmit and
receive data.
The frame sync (SYNC) is asserted for one "serial word length" which
determined by CFGH[8:11].
The frame sync rate (sampling rate) and SCLK frequency follow equations
(5.1.6b) and (5.1.6a) respectively on master mode and determined by external
devices on slave mode.
The transmit FIFO and receive FIFO is configured as 48x16 if "serial word
length" <= 16, and will be configured as 24x32 if "serial word length" > 16.
The shifting data bits on SDI and SDO are always MSB first.
If serial word length is not 16 or 32, it is software responsibility to left(MSB)
justify the transmit data words before writing it to transmit FIFO, the received
data before being written into receive FIFO is right(LSB) justified automatically
by SSI module where the unfilled MSBs are filled with logic 0s.
SSI module always shifts out logic 0s on each frame sync if transmit FIFO is
empty at that time.
A receiver FIFO interrupt will be asserted (when RX-FIFO interrupt is enable) if
the received data words exceeds the receive FIFO's threshold level. Likewise, a
SCLK frequency = EXTCLK/[2*(CFGL[8:15] + 1)]
SYNC period = SCLK * (CFGL[0:7] + 1)
Serial word length = CFGH[8:11] + 1
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