LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 109

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.19
7.20
7.21
SMSC LPC47M172
LPC Connections
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on
an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on
a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA,
described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode
using program control of the control signals.
Interrupts
The interrupts are enabled by serviceIntr in the ecr register.
serviceIntr = 1
serviceIntr = 0
An interrupt is generated when:
1.
2.
3.
4.
FIFO Operation
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port
can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO
is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be
addressed separately.)
Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to
15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster
servicing of the request for both read and write cases. The host must be very responsive to the service
request. This is the desired case for use with a “fast” system. A high value of threshold (i.e. 12) is used
with a “sluggish” system by affording a long latency period after a service request, but results in more
frequent service requests.
For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.
For Programmed I/O:
When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and
nFault is asserted.
When ackIntEn is 1 and the nAck signal transitions from a low to a high.
a.
b.
When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free
bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever
there are writeIntrThreshold or more free bytes in the FIFO.
When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in
the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are
readIntrThreshold or more bytes in the FIFO.
Disables the DMA and all of the service interrupts.
Enables the selected interrupt condition. If the interrupting condition is valid, then the
interrupts generated immediately when this bit is changed from a 1 to a 0. This can occur
during Programmed I/O if the number of bytes removed or added from/to the FIFO does not
cross the threshold.
After a reset, the FIFO is disabled.
DATASHEET
Page 109
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Each data byte is transferred by a
Datasheet