LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 3

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

LPC47M172 Datasheet Revision History
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
REVISION LEVEL
Rev. 02-27-04
Rev. 02-27-04
Rev. 02-27-04
Rev. 02-26-04
Rev. 02-23-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
AND DATE
Table 12.2 - S3-S5 Standby Current, page
201
Ordering Information
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Chapter 1 - General Description, page 12
Chapter 12 - Electrical Characteristics,
page 196
Section 3.1 - Buffer Name Descriptions,
page 23
Table 3.1 - LPC47M172 Pin Description,
page 15
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Table 7.31 - Voltage Translation DDC Pins,
page 137
Figure 7.10 - VGA DDC Voltage
Translation Circuit, page 139
Table 7.34 - SMBus Isolation Pins, page
139
Figure 7.11 - SMBUS Isolation Circuit,
page 140
Table 12.1 - Operational DC
Characteristics, page 196
Table 7.7 - Programming for Configuration
Register B (Bits 5:3), page 106; Table 7.8 -
Programming for Configuration Register B
(Bits 2:0), page 106
Table 11.2 - LPC47M172 Configuration
Register Summary, page 178
Table 11.3 - Chip Level Registers, page
180
Chapter 2 - Pin Layout, page 13
Table 3.1 - LPC47M172 Pin Description,
page 15
Chapter 8 Power Control Runtime
Registers, page 151
Chapter 9 GPIO Runtime Registers, page
158
Chapter 10 Runtime Register Block
Runtime Registers, page 162
Table 11.3 - Chip Level Registers, page
180
SECTION/FIGURE/ENTRY
DATASHEET
Page 3
Added note above table.
Added.
Revised heading to include “standard
SMSC” and “non-standard SMSC” register
sets.
Revised General Description adding AMI
BIOS to keyboard interface.
Lead Temperature Range, lead and lead-
free; reference to spec name J-STD-020B.
Added I0_SW.
Buffer names revised for pins 87 – 90,
113 – 116.
Note 8 under table revised.
Added table.
Replaced buffer IOD8 with IO_SW.
Revised figure.
Replaced buffer IOD8 with IO_SW.
First paragraph under table revised.
Revised figure.
Added IO_SW buffer and description;
updated parameters for Icc and Itr.
Titles added to tables.
Value of TEST 7 reg for LD_NUM=1
changed to 0x01.
Definition of TEST 7 value:
Default = 0x00 (when pin 117 is NC), 0x01
(when pin 117 is connected to VTR) on
VCC POR, VTR POR, and HARD RESET
Note for pin 117
No Connect Pin 117,
Pin 117 described in Note 11.
Table added.
Table added.
Added paragraph describing runtime
registers tables.
Register 0x29
Advanced I/O Controller with Motherboard GLUE Logic
CORRECTION
SMSC LPC47M172
Datasheet
TM